KSZ8895MQ/RQ/FMQ
Integrated 5-Port 10/100 Managed Ethernet
Switch with MII/RMII Interface
Revision 1.7
General Description
The KSZ8895MQ/RQ/FMQ is a highly-integrated,
Layer 2 managed, five-port switch with numerous
features designed to reduce system cost. Intended for
cost-sensitive 10/100Mbps five-port switch systems
with low power consumption, on-chip termination, and
internal core power controllers, it supports
high-performance memory bandwidth and shared
memory-based switch fabric with non-blocking
configuration. Its extensive feature set includes power
management, programmable rate limit and priority
ratio, tag/port-based VLAN, packets filtering,
four-queue QoS prioritization, management interfaces,
and MIB counters. The KSZ8895 family provides
multiple CPU data interfaces to effectively address
both current and emerging fast Ethernet applications
when port 5 is configured to separate MAC5 with
SW5-MII/RMII and PHY5 with P5-MII/RMII interfaces.
The KSZ8895 family offers three configurations,
providing the flexibility to meet different requirements:
•
KSZ8895MQ: Five 10/100Base-T/TX transceivers,
one SW5-MII and one P5-MII interface,
•
KSZ8895RQ: Five 10/100Base-T/TX transceivers,
one SW5-RMII and one P5-RMII interface
•
KSZ8895FMQ: Three 10/100Base-T/TX
transceivers on Ports 1, 2, 5 and two 100Base-FX
transceivers on Ports 3, 4, one SW5-MII and one
P5-MII interface
All registers of MACs and PHYs units can be
managed by the SPI or the SMI interface. MIIM
registers can be accessed through the MDC/MDIO
interface. EEPROM can set all control registers for the
unmanaged mode. KSZ8895MQ/RQ/FMQ are 128-pin
PQFP packages.
Functional Diagram
Note:
SW5 indicates the MAC5 of the switch side, P5 indicates the PHY5 of the Port 5.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
March 19, 2014
Revision 1.7
Micrel, Inc.
KSZ8895MQ/RQ/FMQ
Features
Advanced Switch Features
•
On-chip 64Kbyte memory for frame buffering (not shared with
1K unicast address table).
•
IEEE 802.1q VLAN support for up to 128 active VLAN groups
(full-range 4096 of VLAN IDs).
•
•
Full duplex IEEE 802.3x flow control (PAUSE) with force
mode option.
Static MAC table supports up to 32 entries.
•
•
Half-duplex back pressure flow control.
VLAN ID tag/untag options, per port basis
•
•
HP Auto MDI/MDI-X and IEEE Auto crossover support.
IEEE 802.1p/q tag insertion or removal on a per port basis
based on ingress port (egress).
•
SW-MII interface supports both MAC mode and PHY mode.
•
Programmable rate limiting at the ingress and egress on a per
port basis.
•
7-wire serial network interface (SNI) support for legacy MAC.
•
Per port LED Indicators for link, activity, and 10/100 speed.
•
Jitter-free per packet based rate limiting support.
•
•
Broadcast storm protection with percentage control (global
and per port basis).
Register port status support for link, activity, full/half duplex
and 10/100 speed.
•
•
IEEE 802.1d rapid spanning tree protocol RSTP support.
On-chip terminations and internal biasing technology for cost
down and lowest power consumption.
•
Tail tag mode (1 byte added before FCS) support at Port 5 to
inform the processor which ingress port receives the packet.
•
1.4Gbps high-performance memory bandwidth and shared
memory-based switch fabric with fully
non-blocking configuration.
•
Dual MII with MAC5 and PHY5 on port 5, SW5-MII/RMII for
MAC 5 and P5-MII/RMII for PHY 5.
•
Enable/Disable option for huge frame size up to 2000 Bytes
per frame.
•
Interrupt for the link change on any ports.
Low Power Dissipation
•
IGMP v1/v2 snooping (Ipv4) support for multicast packet
filtering.
•
Full-chip hardware power-down.
•
Full-chip software power-down and per port software power
down.
•
Energy-detect mode support < 100mW full chip-power
consumption when all ports have no activity.
•
Self-address filtering.
Comprehensive Configuration Register Access
•
Very low full chip power consumption (5ms) when using this internal 1.2V LDO controller. You can also
use an external 1.2V LDO when 3.3V power ramp time is slow.
Pull-up to enable LDO_O of pin 125. Pull-down to disable LDO_0.
Note: A 4.3K pull-up and a 1K pull-down resistor divider is
recommended if using the internal 1.2V LDO controller plus an
external MOSFET for 1.2V power.
Analog ground.
NC for normal operation. Factory test pin.
pin otherwise.
IPU/O = Input w/internal pull-up during reset, output pin
otherwise.
NC = No connect.
2.
PU = Strap pin pull-up.
PD = Strap pull-down.
OTRI = Output tristated.
P = Power supply.
I = Input.
O = Output.
I/O = Bidirectional.
GND = Ground.
IPU = Input w/internal pull-up.
IPD = Input w/internal pull-down.
IPD/O = Input w/internal pull-down during reset, output
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KSZ8895MQ/RQ/FMQ
Pin for Strap-In Options
The KSZ8895MQ/RQ/FMQ can function as a managed switch or an unmanaged switch. If no EEPROM or microcontroller exists, then the KSZ8895MQ/RQ/FMQ will operate from its default setting. The strap-in option pins can be
configured by external pull-up/down resistors and take effect after power down reset or warm reset. The functions are
described in the following table.
(1)
Pin #
Pin Name
PU/PD
1
MDI-XDIS
IPD
62
PMRXD3
IPD/O
63
PMRXD2
IPD/O
64
PMRXD1
IPD/O
65
PMRXD0
IPD/O
66
PMRXER
IPD/O
67
PCRS
IPD/O
68
PCOL
IPD/O
80
SMRXD3
IPD/O
81
SMRXD2
IPD/O
82
SMRXD1
IPD/O
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(1)
Description
Disable auto MDI/MDI-X.
Strap option:
PD = (default) = normal operation.
PU = disable auto MDI/MDI-X on all ports.
PHY[5] MII receive bit 3.
Strap option:
PD (default) = enable flow control;
PU = disable flow control.
PHY[5] MII receive bit 2.
Strap option:
PD (default) = disable back pressure;
PU = enable back pressure.
PHY[5] MII receive bit 1.
Strap option:
PD (default) = drop excessive collision packets;
PU = does not drop excessive collision packets.
PHY[5] MII receive bit 0.
Strap option:
PD (default) = disable aggressive back-off algorithm in half-duplex mode;
PU = enable for performance enhancement.
PHY[5] MII receive error.
Strap option:
PD (default) = 1522/1518 bytes;
PU = packet size up to 1536 bytes.
PHY[5] MII carrier sense
Strap option for Port 4 only.
PD (default) = force half-duplex if auto-negotiation is disabled or fails.
PU = force full-duplex if auto-negotiation is disabled or fails. Refer to register 76.
PHY[5] MII collision detect
Strap option for Port 4 only.
PD (default) = no force flow control.
PU = force flow control. Refer to register 66.
Switch MII receive bit 3.
Strap option:
PD (default) = disable switch SW5-MII full-duplex flow control;
PU = enable switch SW5-MII full-duplex flow control.
Switch MII receive bit 2.
Strap option:
PD (default) = switch SW5-MII in full-duplex mode;
PU = switch SW5-MII in half-duplex mode.
Switch MII receive bit 1.
Strap option:
PD (default) = switch SW5-MII in 100Mbps mode.
PU = switch MII in 10Mbps mode.
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Pin for Strap-In Options (Continued)
Pin #
Pin Name
(1)
PU/PD
(1)
Description
Switch MII receive bit 0.
Strap option: LED mode PD (default) = mode 0; PU = mode 1. See “Register
11.”
83
SMRXD0
Mode 0
Mode 1
LEDX_2
Lnk/Act
100Lnk/Act
LEDX_1
Fulld/Col
10Lnk/Act
LEDX_0
Speed
Fulld
IPD/O
Pin 91,86,87 are dual MII/RMII configuration pins for the Port 5 MAC 5 MII/RMII
and PHY[5] MII/RMII. SW5-MII supports both MAC mode and PHY modes. P5MII supports PHY mode only. See pins configuration below.
Port 5 MAC 5 Switch
Port 5 PHY [5]
Pins [91, 86, 87]
SW5-MII
MII/RMII P5-MII/RMII
86
87
SCONF1
SCONF0
IPD
IPD
90
LED5-2
IPU/O
91
LED5-1
IPU/O
92
LED5-0
IPU/O
95
LED4-0
IPU/O
98
LED3-0
IPU/O
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000
Disable, Otri
Disable, Otri
001
PHY Mode MII or RMII
Disable, Otri
010
MAC Mode MII or RMII
Disable, Otri
011
PHY Mode SNI
Disable, Otri
100
Disable
Disable
101
PHY Mode MII or RMII
P5- MII/RMII
110
MAC Mode MII or RMII
P5- MII/RMII
111
PHY Mode SNI
P5- MII/RMII
Dual MII/RMII configuration pin. See pin 86 description.
LED5 indicator 2.
Strap option: Aging setup. See “Aging” section
PU (default) = aging enable;
PD = aging disable.
LED5 indicator 1.
Strap option:
PU (default): enable PHY[5] MII I/F.
PD: tristate all PHY[5] MII output. See “Pin 86 SCONF1.”
LED5 indicator 0.
Strap option for Port 4 only.
PU (default) = Enable auto-negotiation.
PD = Disable auto-negatiation. Strap to register76 bit[7].
LED indicator 0.
Strap option:
PU (default) = Normal mode.
PD = Energy Detection mode (EDPD mode).
Strap to register 14 bits[4:3].
LED3 indicator 0.
Strap option:
PU (default) = Select I/O current drive strength (8mA);
PD = Select I/O current drive strength (12mA).
Strap to register132 bit[7:6].
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Pin for Strap-In Options (Continued)
Pin #
Pin Name
(1)
PU/PD
101
LED2-2
IPU/O
102
LED2-1
IPU/O
105
LED1-1
IPU/O
106
LED1-0
IPU/O
113
PS1
IPD
(1)
Description
LED2 indicator 2.
Strap option for KSZ8895RQ only:
PU (default) = Select the device as clock mode in RQ SW5- RMII, 25MHz
crystal to X1/X2 pins of the device and REFCLK output 50MHz clock.
PD = Select the device as normal mode in SW5-RMII. Switch MAC5 used only.
The input clock is useless from X1/X2 pin, the device’s clock comes from
SMTXC/SMREFCLK pin, 50MHz reference clock from external 50MHz clock
source.
LED2 indicator 1.
Strap option for Port 3 only.
PU (default) = Enable auto-negotiation.
PD = Disable auto-negatiation.
Strap to register60 bit[7].
LED1 indicator 1.
Strap option for Port 3 only.
PU (default) = no force flow control, normal operation.
PD = force flow control. Strap to register50 bit[4].
LED1 indicator 0.
Strap option for Port 3 only.
PU (default) = force half-duplex if auto-negotiation is disabled or fails.
PD = force full-duplex if auto negotiation is disabled or fails.
Strap to register60 bit[5].
Serial bus configuration pin. For this case, if the EEPROM is not present, the
KSZ8895MQ/RQ/FMQ will start itself with the PS[1:0] = 00 default register
values .
Pin Configuration
Serial Bus Configuration
2
PS[1:0] = 00
I C Master Mode for EEPROM
PS[1:0] = 01
SMI Interface Mode
PS[1:0] = 10
SPI Slave Mode for CPU Interface
PS[1:0] = 11
Factory Test Mode (BIST)
114
PS0
IPD
Serial bus configuration pin. See “Pin 113.”
128
TEST2
NC
NC for normal operation. Factory test pin.
Note:
1. NC = No connect.
IPD = Input w/internal pull-down.
IPD/O = Input w/internal pull-down during reset, output pin otherwise.
IPU/O = Input w/internal pull-up during reset, output pin otherwise.
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KSZ8895MQ/RQ/FMQ
Introduction
The KSZ8895MQ/RQ/FMQ contains five 10/100 physical layer transceivers and five media access control (MAC)
units with an integrated Layer 2 managed switch. The device runs in three modes. The first mode is as a five-port
integrated switch. The second is as a five-port switch with the fifth port decoupled from the physical port. In this
mode, access to the fifth MAC is provided through a media independent interface (MII/RMII). This is useful for
implementing an integrated broadband router. The third mode uses the dual MII/RMII feature to recover the use of
the fifth PHY. This allows the additional broadband gateway configuration, where the fifth PHY may be accessed
through the P5-MII/RMII port.
The KSZ8895MQ/RQ/FMQ has the flexibility to reside in a managed or unmanaged design. In a managed design, a
host processor has complete control of the KSZ8895MQ/RQ/FMQ via the SPI bus, or the MDC/MDIO interface. An
unmanaged design is achieved through I/O strapping or EEPROM programming at system reset time.
On the media side, the KSZ8895MQ/RQ/FMQ supports IEEE 802.3 10BASE-T, 100BASE-TX on all copper ports
with Auto MDI/MDIX. The KSZ8895FMQ supports 100BASE-FX on port 3 and port 4. The KSZ8895MQ/RQ/FMQ can
be used as a fully managed five-port switch or hooked up to a microprocessor by its SW-MII/RMII interfaces for any
application solutions.
Physical signal transmission and reception are enhanced through the use of patented analog circuitry that makes the
design more efficient and allows for reduced power consumption and smaller chip die size.
Major enhancements from the KS8895MA/FQ to the KSZ8895MQ/RQ/FMQ include more host interface options, a
dual-switch MAC5 MII and PHY5 MII interfaces with other options, RMII from part of the KSZ8895RQ, tag and portbased VLAN, rapid spanning tree support, IGMP snooping support, port mirroring support, more flexible rate limiting,
and new filtering functionality.
Functional Overview: Physical Layer Transceiver
100BASE-TX Transmit
The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI
conversion, MLT3 encoding and transmission. The circuit starts with a parallel-to-serial conversion, which converts
the MII data from the MAC into a 125MHz serial bit stream. The data and control stream is then converted into 4B/5B
coding followed by a scrambler. The serialized data is further converted from NRZ-to-NRZI format, and then
transmitted in MLT3 current output. The output current is set by an external 1% 12.4kΩ resistor for the 1:1
transformer ratio. It has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding
amplitude balance, overshoot, and timing jitter. The wave-shaped 10BASE-T output is also incorporated into the
100BASE-TX transmitter.
100BASE-TX Receive
The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data
and clock recovery, NRZI-to-NRZ conversion, descrambling, 4B/5B decoding, and serial-to-parallel conversion. The
receiving side starts with the equalization filter to compensate for intersymbol interference (ISI) over the twisted pair
cable. Since the amplitude loss and phase distortion is a function of the length of the cable, the equalizer has to
adjust its characteristics to optimize the performance. In this design, the variable equalizer will make an initial
estimation based on comparisons of incoming signal strength against some known cable characteristics, then tunes
itself for optimization. This is an ongoing process and can self-adjust against environmental changes such as
temperature variations.
The equalized signal then goes through a DC restoration and data conversion block. The DC restoration circuit is
used to compensate for the effect of baseline wander and improve the dynamic range. The differential data
conversion circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then
used to convert the NRZI signal into the NRZ format. The signal is then sent through the de-scrambler followed by
the 4B/5B decoder. Finally, the NRZ serial data is converted to the MII format and provided as the input data to the
MAC.
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KSZ8895MQ/RQ/FMQ
PLL Clock Synthesizer
The KSZ8895MQ/RQ/FMQ generates 125MHz, 83MHz, 41MHz, 25MHz and 10MHz clocks for system timing.
Internal clocks are generated from an external 25MHz crystal or oscillator.
Scrambler/Descrambler (100BASE-TX only)
The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline
wander. The data is scrambled through the use of an 11-bit wide linear feedback shift register (LFSR). This can
generate a 2047-bit non-repetitive sequence. The receiver will then descramble the incoming data stream with the
same sequence at the transmitter.
100BASE-FX Operation
100BASE-FX operation is very similar to 100BASE-TX operation except that the scrambler/descrambler and MLT3
encoder/decoder are bypassed on transmission and reception. In this mode, the auto-negotiation feature is bypassed
since there is no standard that supports fiber auto-negotiation.
100BASE-FX Signal Detection
The physical port runs in 100BASE-FX fiber mode for the Port 3 and Port 4 of the KSZ8895FMQ. This signal is
internally referenced to 1.2V. The fiber module interface should be set by a voltage divider such that FXSDx ‘H’ is
above this 1.2V reference, indicating signal detect, and FXSDx ‘L’ is below the 1.2V reference to indicate no signal.
There is no auto-negotiation for 100BASE-FX mode, the ports must be forced to either full or half-duplex for the fiber
ports. Note that strap-in options support Port 3 and Port 4 to disable auto-negotiation, force 100Base-FX speed, force
duplex mode, and force flow control for KSZ8895FMQ with unmanaged mode.
100BASE-FX Far End Fault
Far end fault occurs when the signal detection is logically false from the receive fiber module. When this occurs, the
transmission side signals the other end of the link by sending 84 1s followed by a zero in the idle period between
frames.
10BASE-T Transmit
The output 10BASE-T driver is incorporated into the 100BASE-T driver to allow transmission with the same
magnetics. They are internally wave-shaped and pre-emphasized into outputs with a typical 2.3V amplitude. The
harmonic contents are at least 27dB below the fundamental when driven by an all-ones Manchester-encoded signal.
10BASE-T Receive
On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit
and a PLL perform the decoding function. The Manchester-encoded data stream is separated into clock signal and
NRZ data. A squelch circuit rejects signals with levels less than 400mV or with short pulsewidths in order to prevent
noises at the RXP or RXM input from falsely triggering the decoder. When the input exceeds the squelch limit, the
PLL locks onto the incoming signal and the KSZ8895MQ/RQ/FMQ decodes a data frame. The receiver clock is
maintained active during idle periods in between data reception.
MDI/MDI-X Auto Crossover
To eliminate the need for crossover cables between similar devices, the KSZ8895MQ/RQ/FMQ supports HP Auto MDI/MDI-X
and IEEE 802.3u standard MDI/MDI-X auto crossover. HP Auto MDI/MDI-X is the default.
The auto-sense function detects remote transmit and receive pairs and correctly assigns transmit and receive pairs for the
KSZ8895MQ/RQ/FMQ device. This feature is extremely useful when end users are unaware of cable types, and also, saves on
an additional uplink configuration connection. The auto-crossover feature can be disabled through the port control registers, or
MIIM PHY registers. The IEEE 802.3u standard MDI and MDI-X definitions are:
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KSZ8895MQ/RQ/FMQ
MDI
MDI-X
RJ-45 Pins
Signals
RJ-45 Pins
Signals
1
TD+
1
RD+
2
TD-
2
RD-
3
RD+
3
TD+
6
RD-
6
TD-
Table 1. MDI/MDI-X Pin Definitions
Straight Cable
A straight cable connects an MDI device to an MDI-X device, or an MDI-X device to an MDI device. Figure 6 depicts
a typical straight cable connection between a NIC card (MDI) and a switch, or hub (MDI-X).
Figure 6. Typical Straight Cable Connection
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Crossover Cable
A crossover cable connects an MDI device to another MDI device, or an MDI-X device to another MDI-X device.
Figure 7 shows a typical crossover cable connection between two switches or hubs (two MDI-X devices).
Figure 7. Typical Crossover Cable Connection
Auto-Negotiation
The KSZ8895MQ/RQ/FMQ conforms to the auto-negotiation protocol as described by the 802.3 committee. Autonegotiation allows unshielded twisted pair (UTP) link partners to select the highest common mode of operation. Link
partners advertise their capabilities to each other, and then compare their own capabilities with those they received
from their link partners. The highest speed and duplex setting that is common to the two link partners is selected as
the mode of operation. Auto-negotiation is supported for the copper ports only.
The following list shows the speed and duplex operation mode from highest to lowest.
•
Highest: 100Base-TX, full-duplex
•
High:
100Base-TX, half-duplex
•
Low:
10Base-T, full-duplex
•
Lowest: 10Base-T, half-duplex
If auto-negotiation is not supported or the KSZ8895MQ/RQ/FMQ link partner is forced to bypass auto-negotiation, the
KSZ8895MQ/RQ/FMQ sets its operating mode by observing the signal at its receiver. This is known as parallel
detection, and allows the KSZ8895MQ/RQ/FMQ to establish link by listening for a fixed signal protocol in the
absence of auto-negotiation advertisement protocol. The auto-negotiation link up process is shown in Figure 8.
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KSZ8895MQ/RQ/FMQ
Figure 8. Auto-Negotiation
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On-Chip Termination Resistors
The KSZ8895MQ/RQ/FMQ reduces the board cost and simplifies the board layout by using on-chip termination
resistors for all ports and RX/TX differential pairs without the external termination resistors. The combination of the
on-chip termination and internal biasing will save about 500 to 1000mw in power consumption as compared to using
external biasing and termination resistors, and the transformer will not consume power any more. The center tap of
the transformer does not need to be tied to the analog power and does not tie the center taps together between RX
and TX pairs for its application.
Internal 1.2V LDO Controller
The KSZ8895MQ/RQ/FMQ reduces board cost and simplifies board layout by integrating an internal 1.2V LDO
controller to drive a low cost MOSFET to supply the 1.2V core power voltage for a single 3.3V power supply solution.
The internal 1.2V LDO controller can be disabled by pin 126 IN_PWR_SEL pull-down in order to use an external
1.2V LDO.
Functional Overview: Power Management
The KSZ8895MQ/RQ/FMQ supports a full chip hardware power down mode. When the PWRDN pin 47 is internally
activated low (pin PWRDN = 0), the entire chip is powered down. If this pin is de-asserted, the chip will be reset
internally.
The KSZ8895MQ/RQ/FMQ can also use multiple power levels of 3.3V, 2.5V or 1.8V for VDDIO to support different
I/O voltage.
The KSZ8895MQ/RQ/FMQ supports enhanced power management in a low power state, with energy detection to
ensure low power dissipation during device idle periods. There are five operation modes under the power
management function which are controlled by the Register 14 bit[4:3] and the Port Register Control 13 bit 3 as shown
below:
Register 14 bit [4:3] = 00 Normal Operation Mode
Register 14 bit [4:3] = 01 Energy Detect Mode
Register 14 bit [4:3] = 10 Soft Power Down Mode
Register 14 bit [4:3] = 11 Power Saving Mode
The Port Register 29, 45, 61, 77, 93 Control 13 bit 3 = 1 are for the Port Based Power-Down Mode.
Table 2 indicates all internal function blocks’ status under four different power management operation modes.
Power Management Operation Modes
KSZ8895MQ/RQ/FMQ
Function Blocks
Normal Mode
Power Saving Mode
Energy Detect Mode
Soft Power Down Mode
Internal PLL Clock
Enabled
Enabled
Disabled
Disabled
Tx/Rx PHY
Enabled
Rx unused block disabled
Energy detect at Rx
Disabled
MAC
Enabled
Enabled
Disabled
Disabled
Host Interface
Enabled
Enabled
Disabled
Disabled
Table 2. Internal Function Block Status
Normal Operation Mode
This is the default setting bit [4:3] = 00 in register 14 after chip power-up or hardware reset. When
KSZ8895MQ/RQ/FMQ is in normal operation mode, all PLL clocks are running, PHY and MAC are on, and the host
interface will be ready for CPU read or write.
During normal operation mode, the host CPU can set the bit [4:3] in register 14 to change the current normal
operation mode to any one of the other three power management operation modes.
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Energy Detect Mode
Energy detect mode provides a mechanism to save more power than in the normal operation mode when the
KSZ8895MQ/RQ/FMQ port is not connected to an active link partner. In this mode, the device will save more power
when the cables are unplugged. If the cable is not plugged in, the device can automatically enter a low power state—
the energy detect mode. In this mode, the device will keep transmitting 120ns width pulses at 1 pulse/s rate. Once
activity resumes due to plugging a cable in or attempting by the far end to establish link, the device can automatically
power up to normal power state in energy detect mode.
Energy detect mode consists of two states, normal power state and low power state. While in low power state, the
device reduces power consumption by disabling all circuitry except the energy detect circuitry of the receiver. The
energy detect mode is entered by setting bit [4:3] = 01 in register 14. When the KSZ8895MQ/RQ/FMQ is in this
mode, it will monitor the cable energy. If there is no energy on the cable for a time longer than the pre-configured
value at bit [7:0] Go-Sleep time in register 15, KSZ8895MQ/RQ/FMQ will go into low power state. When
KSZ8895MQ/RQ/FMQ is in low power state, it will keep monitoring the cable energy. Once the energy is detected
from the cable, the device will enter normal power state. When the device is at normal power state, it is able to
transmit or receive packet from the cable.
Soft Power Down Mode
The soft power down mode is entered by setting bit [4:3] = 10 in register 14. When KSZ8895MQ/RQ/FMQ is in this
mode, all PLL clocks are disabled, also all of PHYs and the MACs are off. Any dummy host access will wake-up this
device from current soft power down mode to normal operation mode and internal reset will be issued to make all
internal registers go to the default values.
Power Saving Mode
The power saving mode is entered when auto-negotiation mode is enabled, the cable is disconnected, and by setting
bit[4:3] = 11 in register 14. When KSZ8895MQ/RQ/FMQ is in this mode, all PLL clocks are enabled, MAC is on, all
internal register values will not change, and the host interface is ready for CPU read or write. In this mode, it mainly
controls the PHY transceiver on or off, based on line status to achieve power saving. The PHY continues to transmit,
only turning off the unused receiver block. Once activity resumes, due to plugging a cable or attempting by the far
end to establish link, the KSZ8895MQ/RQ/FMQ can automatically enable the PHY to power up to normal power state
from power saving mode.
During power saving mode, the host CPU can set bit [4:3] in register 14 to change the current power saving mode to
any one of the other three power management operation modes.
Port-based Power Down Mode
In addition, the KSZ8895MQ/RQ/FMQ features a per-port power down mode. To save power, a PHY port that is not
in use can be powered down via the port registers control 13 bit 3, or MIIM PHY registers 0 bit 11.
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Functional Overview: Switch Core
Address Look-Up
The internal look-up table stores MAC addresses and their associated information. It contains a 1K unicast address
table plus switching information. The KSZ8895MQ/RQ/FMQ is guaranteed to learn 1K addresses and distinguishes
itself from a hash-based look-up table, which, depending on the operating environment and probabilities, may not
guarantee the absolute number of addresses it can learn.
Learning
The internal look-up engine updates its table with a new entry if the following conditions are met:
• The received packet’s source address (SA) does not exist in the look-up table.
• The received packet is good; the packet has no receiving errors and is of legal length.
The look-up engine inserts the qualified SA into the table, along with the port number and time stamp. If the table is
full, the last entry of the table is deleted first to make room for the new entry.
Migration
The internal look-up engine also monitors whether a station is moved. If this occurs, it updates the table accordingly.
Migration happens when the following conditions are met:
• The received packet’s SA is in the table but the associated source port information is different.
• The received packet is good; the packet has no receiving errors and is of legal length.
The look-up engine will update the existing record in the table with the new source port information.
Aging
The look-up engine will update the time stamp information of a record whenever the corresponding SA appears. The
time stamp is used in the aging process. If a record is not updated for a period of time, the look-up engine will
remove the record from the table. The look-up engine constantly performs the aging process and will continuously
remove aging records. The aging period is 300 +/- 75 seconds. This feature can be enabled or disabled through
Register 3 or by external pull-up or pull-down resistors on LED[5][2]. See “Register 3” section.
Forwarding
The KSZ8895MQ/RQ/FMQ will forward packets using an algorithm that is depicted in the following flowcharts. Figure
6 shows stage one of the forwarding algorithm where the search engine looks up the VLAN ID, static table, and
dynamic table for the destination address, and comes up with “port to forward 1” (PTF1). PTF1 is then further
modified by the spanning tree, IGMP snooping, port mirroring, and port VLAN processes to come up with “port to
forward 2” (PTF2), as shown in Figure 7. This is where the packet will be sent.
KSZ8895MQ/RQ/FMQ will not forward the following packets:
•
Error packets. These include framing errors, FCS errors, alignment errors, and illegal size packet errors.
•
802.3x pause frames. The KSZ8895MQ/RQ/FMQ will intercept these packets and perform the appropriate
actions.
•
“Local” packets. Based on destination address (DA) look-up. If the destination port from the look-up table
matches the port where the packet was from, the packet is defined as “local.”
Switching Engine
The KSZ8895MQ/RQ/FMQ features a high-performance switching engine to move data to and from the MAC’s
packet buffers. It operates in store and forward mode, while the efficient switching mechanism reduces overall
latency. The KSZ8895MQ/RQ/FMQ has a 64kB internal frame buffer. This resource is shared between all five ports.
There are a total of 512 buffers available. Each buffer is sized at 128B.
Media Access Controller (MAC) Operation
The KSZ8895MQ/RQ/FMQ strictly abides by IEEE 802.3 standards to maximize compatibility.
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Inter-Packet Gap (IPG)
If a frame is successfully transmitted, the 96-bit time IPG is measured between the two consecutive MTXEN. If the
current packet is experiencing collision, the 96-bit time IPG is measured from MCRS and the next MTXEN.
Backoff Algorithm
The KSZ8895MQ/RQ/FMQ implements the IEEE Standard 802.3 binary exponential backoff algorithm, and optional
“aggressive mode” backoff. After 16 collisions, the packet will be optionally dropped, depending on the chip
configuration in Register 3. See “Register 3.”
Late Collision
If a transmit packet experiences collisions after 512-bit times of the transmission, the packet will be dropped.
Illegal Frames
The KSZ8895MQ/RQ/FMQ discards frames less than 64 bytes and can be programmed to accept frames up to 1536
bytes in Register 4. For special applications, the KSZ8895MQ/RQ/FMQ can also be programmed to accept frames
up to 1916 bytes in Register 4. Since the KSZ8895MQ/RQ/FMQ supports VLAN tags, the maximum sizing is
adjusted when these tags are present.
Flow Control
The KSZ8895MQ/RQ/FMQ supports standard 802.3x flow control frames on both transmit and receive sides.
On the receive side, if the KSZ8895MQ/RQ/FMQ receives a pause control frame, the KSZ8895MQ/RQ/FMQ will not
transmit the next normal frame until the timer, specified in the pause control frame, expires. If another pause frame is
received before the current timer expires, the timer will be updated with the new value in the second pause frame.
During this period (being flow controlled), only flow control packets from the KSZ8895MQ/RQ/FMQ will be
transmitted.
On the transmit side, the KSZ8895MQ/RQ/FMQ has intelligent and efficient ways to determine when to invoke flow
control. The flow control is based on availability of the system resources, including available buffers, available
transmit queues and available receive queues.
The KSZ8895MQ/RQ/FMQ flow controls a port that has just received a packet if the destination port resource is
busy. The KSZ8895MQ/RQ/FMQ issues a flow control frame (XOFF), containing the maximum pause time defined in
IEEE standard 802.3x. Once the resource is freed up, the KSZ8895MQ/RQ/FMQ sends out the other flow control
frame (XON) with zero pause time to turn off the flow control (turn on transmission to the port). A hysteresis feature is
also provided to prevent over-activation and deactivation of the flow control mechanism.
The KSZ8895MQ/RQ/FMQ flow controls all ports if the receive queue becomes full.
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Figure 9. Destination Address Lookup Flow Chart, Stage 1
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Figure 10. Destination Address Resolution Flow Chart, Stage 2
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The KSZ8895MQ/RQ/FMQ will not forward the following packets:
1. Error packets
These include framing errors, Frame Check Sequence (FCS) errors, alignment errors, and illegal size packet
errors.
2. IEEE802.3x PAUSE frames
KSZ8895MQ/RQ/FMQ intercepts these packets and performs full duplex flow control accordingly.
3. "Local" packets
Based on destination address (DA) lookup, if the destination port from the lookup table matches the port from
which the packet originated, the packet is defined as "local."
Half-Duplex Back Pressure
The KSZ8895MQ/RQ/FMQ also provides a half-duplex back pressure option (note: this is not in IEEE 802.3
standards). The activation and deactivation conditions are the same as the ones given for full-duplex mode. If back
pressure is required, the KSZ8895MQ/RQ/FMQ sends preambles to defer the other station's transmission (carrier
sense deference). To avoid jabber and excessive deference as defined in IEEE 802.3 standards, after a certain
period of time, the KSZ8895MQ/RQ/FMQ discontinues carrier sense but raises it quickly after it drops packets to
inhibit other transmissions. This short silent time (no carrier sense) is to prevent other stations from sending out
packets and keeps other stations in a carrier sense-deferred state. If the port has packets to send during a back
pressure situation, the carrier sense-type back pressure is interrupted and those packets are transmitted instead. If
there are no more packets to send, carrier sense-type back pressure becomes active again until switch resources
are free. If a collision occurs, the binary exponential backoff algorithm is skipped and carrier sense is generated
immediately, reducing the chance of further colliding and maintaining carrier sense to prevent reception of packets.
To ensure no packet loss in 10BASE-T or 100BASE-TX half-duplex modes, the user must enable the following:
•
Aggressive backoff (Register 3, bit 0)
•
No excessive collision drop (Register 4, bit 3)
•
Back pressure (Register 4, bit 5)
These bits are not set as the default because this is not the IEEE standard.
Broadcast Storm Protection
The KSZ8895MQ/RQ/FMQ has an intelligent option to protect the switch system from receiving too many broadcast
packets. Broadcast packets are normally forwarded to all ports except the source port and thus use too many switch
resources (bandwidth and available space in transmit queues). The KSZ8895MQ/RQ/FMQ has the option to include
“multicast packets” for storm control. The broadcast storm rate parameters are programmed globally and can be
enabled or disabled on a per port basis. The rate is based on a 50ms (0.05s) interval for 100BT and a 500ms (0.5s)
interval for 10BT. At the beginning of each interval, the counter is cleared to zero and the rate limit mechanism starts
to count the number of bytes during the interval. The rate definition is described in Registers 6 and 7. The default
setting for Registers 6 and 7 is 0x4A (74 decimal). This is equal to a rate of 1%, calculated as follows:
148,80 frames/sec X 50ms (0.05s)/interval X 1% = 74 frames/interval (approx.) = 0x4A
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MII Interface Operation
The media-independent interface (MII) is specified by the IEEE 802.3 committee and provides a common interface
between physical layer and MAC layer devices. The KSZ8895MQ/RQ/FMQ provides two such interfaces. The P5-MII
interface is used to connect to the fifth PHY, where as the SW-MII interface is used to connect to the fifth MAC. Each
of these MII interfaces contains two distinct groups of signals, one for transmission and the other for receiving.
Port 5 PHY 5 P5-MII/RMII Interface
The media independent interface (MII) is specified by the IEEE 802.3 committee and provides a common interface
between the physical layer and MAC layer devices. The Reduced Media Independent Interface (RMII) specifies a low
pin count MII. The KSZ8895MQ/RQ/FMQ provides two such interfaces for MAC5 and PHY5. The Port 5 PHY5 P5MII/RMII interface is used to connect to the fifth PHY, where as the SW-MII/RMII interface is used to connect to the
fifth MAC. The KSZ8895MQ/FMQ support P5-MII, the KSZ8895RQ supports P5-RMII. Each of these MII/RMII
interfaces contains two distinct groups of signals, one for transmission and the other for receiving. Table 3 describes
the signals used in the PHY[5] P5-MII/RMII interface. The P5-MII interface operates in PHY mode only.
MII
Signal
Description
KSZ8895MQ/FMQ
P5-MII
KSZ8895MQ/FMQ
MII Signal Type
KSZ8895RQ
P5-RMII
KSZ8895RQ
RMII Signal
Type
MTXEN
Transmit enable
PMTXEN
I
PMTXEN
I
MTXER
Transmit error
PMTXER
I
MTXD3
Transmit data bit 3
PMTXD[3]
I
MTXD2
Transmit data bit 2
PMTXD[2]
I
MTXD1
Transmit data bit 1
PMTXD[1]
I
PMTXD[1]
I
MTXD0
Transmit data bit 0
PMTXD[0]
I
PMTXD[0]
I
MTXC
Transmit clock
PMTXC
O
PMREFCLK/PMTXC
I
MCOL
Collision detection
PCOL
O
MCRS
Carrier sense
PCRS
O
MRXDV
Receive data valid
PMRXDV
O
PMRXDV
O
MRXER
Receive error
PMRXER
O
PMRXER
O
MRXD3
Receive data bit 3
PMRXD[3]
O
MRXD2
Receive data bit 2
PMRXD[2]
O
MRXD1
Receive data bit 1
PMRXD[1]
O
PMRXD[1]
O
MRXD0
Receive data bit 0
PMRXD[0]
O
PMRXD[0]
O
MRXC
Receive clock
PMRXC
O
PMRXC
O
Table 3. Port 5 PHY P5-MII/RMII Signals
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Port 5 MAC 5 SW5-MII Interface for the KSZ8895MQ/FMQ
Table 4 shows two connection manners:
1. The first is an external MAC connects to SW5-MII PHY mode.
2. The second is an external PHY connects to SW5-MII MAC mode.
Please see the pin [91, 86, 87] descriptions for configuration details for the MAC mode and PHY mode. SW5-MII
works with 25MHz clock for 100Base-TX, SW5-MII works with 2.5MHz clock for 10Base-T.
KSZ8895MQ/RQ/FMQ PHY Mode Connection
KSZ8895MQ/RQ/FMQ MAC Mode Connection
External MAC
KSZ8895MQ/RQ/FMQ
SW5-MII Signals
Type
Description
External
PHY
KSZ8895MQ/RQ/FMQ
SW5-MII Signals
Type
MTXEN
SMTXEN
Input
Transmit enable
MTXEN
SMRXDV
Output
MTXER
SMTXER
Input
Transmit error
MTXER
Not used
Not used
MTXD3
SMTXD[3]
Input
Transmit data bit 3
MTXD3
SMRXD[3]
Output
MTXD2
SMTXD[2]
Input
Transmit data bit 2
MTXD2
SMRXD[2]
Output
MTXD1
SMTXD[1]
Input
Transmit data bit 1
MTXD1
SMRXD[1]
Output
MTXD0
SMTXD[0]
Input
Transmit data bit 0
MTXD0
SMRXD[0]
Output
MTXC
SMTXC
Output
Transmit clock
MTXC
SMRXC
Input
MCOL
SCOL
Output
Collision detection
MCOL
SCOL
Input
MCRS
SCRS
Output
Carrier sense
MCRS
SCRS
Input
MRXDV
SMRXDV
Output
Receive data valid
MRXDV
SMTXEN
Input
MRXER
Not used
Output
Receive error
MRXER
SMTXER
Input
MRXD3
SMRXD[3]
Output
Receive data bit 3
MRXD3
SMTXD[3]
Input
MRXD2
SMRXD[2]
Output
Receive data bit 2
MRXD2
SMTXD[2]
Input
MRXD1
SMRXD[1]
Output
Receive data bit 1
MRXD1
SMTXD[1]
Input
MRXD0
SMRXD[0]
Output
Receive data bit 0
MRXD0
SMTXD[0]
Input
MRXC
SMRXC
Output
Receive clock
MRXC
SMTXC
Input
Table 4. Switch MAC5 MII Signals
The switch MII interface operates in either MAC mode or PHY mode for KSZ8895MQ/RQ/FMQ. These interfaces are
nibble-wide data interfaces, so they run at one-quarter the network bit rate (not encoded). Additional signals on the
transmit side indicate when data is valid or when an error occurs during transmission. Likewise, the receive side has
indicators that convey when the data is valid and without physical layer errors. For half-duplex operation, there is a
signal that indicates a collision has occurred during transmission.
Note that the signal MRXER is not provided on the MII-SW interface for PHY mode operation and the signal MTXER
is not provided on the SW-MII interface for MAC mode operation. Normally MRXER would indicate a receive error
coming from the physical layer device. MTXER would indicate a transmit error from the MAC device. These signals
are not appropriate for this configuration. For PHY mode operation with an external MAC, if the device interfacing
with the KSZ8895MQ/RQ/FMQ has an MRXER pin, it should be tied low. For MAC mode operation with an external
PHY, if the device interfacing with the KSZ8895MQ/RQ/FMQ has an MTXER pin, it should be tied low.
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Port 5 MAC 5 Switch SW5-RMII Interface for the KSZ8895RQ
The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII). The
KSZ8895RQ supports RMII interface at Port 5 switch side and provides a common interface at MAC5 layer in the
device, and has the following key characteristics:
•
Supports 10Mbps and 100Mbps data rates.
•
Uses a single 50MHz clock reference (provided internally or externally): in internal mode, the chip provides a
reference clock from the SMRXC pin to the SMTXC pin and provides the clock to the opposite clock input pin
for RMII interface. In external mode, the chip receives 50MHz reference clock from an external oscillator or
opposite RMII interface.
•
Provides independent 2-bit wide (bi-bit) transmit and receive data paths.
KSZ8895RQ supports MAC5 RMII interfaces at the switch side:
•
For the detail of SW5-RMII (Port 5 MAC5 RMII) signals connection see the table below:
•
The KSZ8895RQ can provide a 50MHz reference clock for both MAC to MAC and MAC to PHY RMII interfaces
when SW5-RMII is used in the clock mode of the device (default with strap pin LED2_2 internal pull-up for the
clock mode).
•
The KSZ8895RQ can also receive a 50MHz reference clock from an external 50MHz clock source or opposite
RMII to SW5-RMII SMTXC pin when the device is set to normal mode (the strap pin LED2_2 is pulled down).
When the device is strapped to normal mode by pin LED2_2 pull-down, the reference clock comes from SMTXC
which will be used as the device’s clock source. The external 25MHz crystal clock from pins X1/X2 will be ignored.
Note: In normal mode, the 50MHz clock from SMTXC will be used as the clock source for whole device. The PHY5
PMTXC/PMREFCLK pin cannot be used as the clock source for whole device. The pin of PMTXC/PMREFCLK can
receive the 50MHz clock from PMRXC when the device is strapped to normal mode and an external 50MHz
reference clock comes in from pin SMTXC. In normal mode, the 50MHz clock on pin SMRXC can be disabled by
register, and the PMRXC 50MHz clock can be used when P5-RMII interface is used.
There is a register 12 bit 6 to monitor the status of the device for the clock mode or normal mode.
When using an external 50MHz clock source as RMII reference clock, the KSZ8895RQ should be set to normal
mode by pulling down its LED2_2 strap-in pin first before power up reset or warm reset. The normal mode of the
KSZ8895RQ device will start to work when it gets the 50MHz reference clock from pin SMTXC/SMREFCLK from an
external 50MHz clock source. For the RMII connection examples, please refer to app note in the design kit.
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SW5-RMII MAC to MAC Connection
(‘PHY mode’)
KSZ8895RQ
External KSZ8895RQ
SW Signal
SW5-RMII
MAC
Type
Output (clock
mode with
50MHz)
(Normal mode
without
connection)
SW5-RMII MAC to PHY Connection
(‘MAC mode’)
External
PHY
KSZ8895RQ
SW5-RMII
Reference Clock
--------
SMTXC/SM
REFCLK
Description
KSZ8895RQ SW
Signal Type
Input (clock comes
from SMRXC in
clock mode or
external clock in
normal mode)
REF_CLK
SMRXC
CRS_DV
SMRXDV
/SMCRSDV
Output
Carier sense/Receive
data valid
CRS_DV
SMTXEN
Input
RXD[1:0]
SMRXD[1:0]
Output
Receive data bit [1:0]
RXD[1:0]
SMTXD[1:0]
Input
Output
Output
TX_EN
SMTXEN
Input
Transmit data enable
TX_EN
SMRXDV
/SMCRSDV
TXD[1:0]
SMTXD[1:0]
Input
Transmit data bit
[1:0]
TXD[1:0]
SMRXD[1:0]
(not used)
(not used)
Receive error
(not used)
(not used)
---
SMTXC/SM
REFCLK
Input (clock
comes from
SMRXC in clock
mode or external
clock in normal
mode)
Reference Clock
REF_CLK
SMRXC
Output (clock mode
with 50MHz)
(Normal mode
without connection)
Note:
1.
MAC/PHY mode in RMII is difference with MAC/PHY mode in MII, there is no strap pin and register configuration request in RMII, just follow
the signals connection in the table.
Table 5. Port 5 MAC5 SW5-RMII Connection
SNI Interface Operation
The serial network interface (SNI) is compatible with some controllers used for network layer protocol processing.
This interface can be directly connected to these types of devices. The signals are divided into two groups, one for
transmission and the other for reception. The signals involved are described in Table below.
SNI Signal
Description
KSZ8895MQ/RQ/FMQ Signal
TXEN
Transmit Enable
SMTXEN
TXD
Serial Transmit Data
SMTXD[0]
TXC
Transmit Clock
SMTXC
COL
Collision Detection
SCOL
CRS
Carrier Sense
SMRXDV
RXD
Serial Receive Data
SMRXD[0]
RXC
Receive Clock
SMRXC
Table 6. SNI Signals
This interface is a bit-wide data interface, so it runs at the network bit rate (not encoded). An additional signal on the
transmit side indicates when data is valid. Likewise, the receive side has an indicator that shows when the data is
valid.
For half-duplex operation there is a signal that indicates a collision has occurred during transmission.
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Advanced Functionality
QoS Priority Support
The KSZ8895MQ/RQ/FMQ provides Quality of Service (QoS) for applications such as VoIP and video conferencing.
The KSZ8895MQ/RQ/FMQ offers one, two, or four priority queues per port by setting the port registers xxx control 9
bit 1 and the port registers xxx control 0 bit 0, the 1/2/4 queues split as follows,
[Port registers xxx control 9 bit 1, control 0 bit 0] = 00 single output queue as default.
[Port registers xxx control 9 bit 1, control 0 bit 0] = 01 egress port can be split into two priority transmit queues.
[Port registers xxx control 9 bit 1, control 0 bit 0] = 10 egress port can be split into four priority transmit queues.
The four priority transmit queue is a new feature in the KSZ8895MQ/RQ/FMQ. The queue 3 is the highest priority
queue and queue 0 is the lowest priority queue. The port registers xxx control 9 bit 1 and the port registers xxx
control 0 bit 0 are used to enable split transmit queues for ports 1, 2, 3, 4 and 5, respectively. If a port's transmit
queue is not split, high priority and low priority packets have equal priority in the transmit queue.
There is an additional option to either always deliver high priority packets first or to use programmable weighted fair
queuing for the four priority queue scale by the port registers control 10, 11, 12 and 13 (default value are 8, 4, 2, 1 by
their bit[6:0].
Register 130 bit[7:6] Prio_2Q[1:0] is used when the 2 Queue configuration is selected, these bits are used to map the
2-bit result of IEEE 802.1p from the registers 128, 129 or TOS/DiffServ mapping from registers 144-159 (for 4
Queues) into two-queue mode with priority high or low.
Please see the descriptions of the register 130 bits [7:6] for detail.
Port-Based Priority
With port-based priority, each ingress port is individually classified as a priority 0-3 receiving port. All packets
received at the priority 3 receiving port are marked as high priority and are sent to the high-priority transmit queue if
the corresponding transmit queue is split. The Port Registers Control 0 Bits[4:3] is used to enable port-based priority
for ports 1, 2, 3, 4 and 5, respectively.
802.1p-Based Priority
For 802.1p-based priority, the KSZ8895MQ/RQ/FMQ examines the ingress (incoming) packets to determine whether
they are tagged. If tagged, the 3-bit priority field in the VLAN tag is retrieved and compared against the “priority
mapping” value, as specified by the registers 128 and 129, both register 128/129 can map 3-bit priority field of 0-7
value to 2-bit result of 0-3 priority levels. The “priority mapping” value is programmable.
Figure 11 illustrates how the 802.1p priority field is embedded in the 802.1Q VLAN tag.
Figure 11. 802.1p Priority Field Format
802.1p-based priority is enabled by bit[5] of the port registers control 0 for ports 1, 2, 3, 4 and 5, respectively.
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The KSZ8895MQ/RQ/FMQ provides the option to insert or remove the priority tagged frame's header at each
individual egress port. This header, consisting of the two-byte VLAN Protocol ID (VPID) and the two-byte Tag Control
Information field (TCI), is also referred to as the IEEE 802.1Q VLAN tag.
Tag Insertion is enabled by bit[2] of the port registers control 0 and the port register control 8 to select which source
port (ingress port) PVID can be inserted on the egress port for ports 1, 2, 3, 4 and 5, respectively. At the egress port,
untagged packets are tagged with the ingress port’s default tag. The default tags are programmed in the port
registers control 3 and control 4 for ports 1, 2, 3, 4 and 5, respectively. The KSZ8895MQ/RQ/FMQ will not add tags
to already tagged packets.
Tag Removal is enabled by bit[1] of the port registers control 0 for ports 1, 2, 3, 4 and 5, respectively. At the egress
port, tagged packets will have their 802.1Q VLAN tags removed. The KSZ8895MQ/RQ/FMQ will not modify untagged
packets.
The CRC is recalculated for both tag insertion and tag removal.
802.1p Priority Field Re-mapping is a QoS feature that allows the KSZ8895MQ/RQ/FMQ to set the “User Priority
Ceiling” at any ingress port by the port register control 2 bit 7. If the ingress packet’s priority field has a higher priority
value than the default tag’s priority field of the ingress port, the packet’s priority field is replaced with the default tag’s
priority field.
DiffServ-Based Priority
DiffServ-based priority uses the ToS registers (registers 144 to 159) in the Advanced Control Registers section. The
ToS priority control registers implement a fully decoded, 128-bit Differentiated Services Code Point (DSCP) register
to determine packet priority from the 6-bit ToS field in the IP header. When the most significant six bits of the ToS
field are fully decoded, 64 code points for DSCP result. These are compared with the corresponding bits in the DSCP
register to determine priority.
Spanning Tree Support
Port 5 is the designated port for spanning tree support.
The other ports (Port 1−Port 4) can be configured in one of the five spanning tree states via “transmit enable,”
“receive enable,” and “learning disable” register settings in Registers 18, 34, 50, and 66 for Ports 1, 2, 3, and 4,
respectively. The following description shows the port setting and software actions taken for each of the five
spanning tree states:
Disable state: the port should not forward or receive any packets. Learning is disabled.
Port setting: "transmit enable = 0, receive enable = 0, learning disable = 1."
Software action: the processor should not send any packets to the port. The switch may still send specific packets to
the processor (packets that match some entries in the static table with “overriding bit” set) and the processor should
discard those packets. Note: the processor is connected to Port 5 via MII interface. Address learning is disabled on
the port in this state.
Blocking state: only packets to the processor are forwarded. Learning is disabled.
Port setting: "transmit enable = 0, receive enable = 0, learning disable = 1"
Software action: the processor should not send any packets to the port(s) in this state. The processor should
program the “Static MAC table” with the entries that it needs to receive (e.g., BPDU packets). The “overriding” bit
should also be set so that the switch will forward those specific packets to the processor. Address learning is
disabled on the port in this state.
Listening state: only packets to and from the processor are forwarded. Learning is disabled.
Port setting: "transmit enable = 0, receive enable = 0, learning disable = 1.
"Software action: The processor should program the static MAC table with the entries that it needs to receive (e.g.
BPDU packets). The “overriding” bit should be set so that the switch will forward those specific packets to the
processor. The processor may send packets to the port(s) in this state, see “Tail Tagging Mode” section for details.
Address learning is disabled on the port in this state.
Learning state: only packets to and from the processor are forwarded. Learning is enabled.
Port setting: “transmit enable = 0, receive enable = 0, learning disable = 0.”
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Software action: The processor should program the static MAC table with the entries that it needs to receive (e.g.,
BPDU packets). The “overriding” bit should be set so that the switch will forward those specific packets to the
processor. The processor may send packets to the port(s) in this state, see “Tail Tagging Mode” section for details.
Address learning is enabled on the port in this state.
Forwarding state: packets are forwarded and received normally. Learning is enabled.
Port setting: “transmit enable = 1, receive enable = 1, learning disable = 0.”
Software action: The processor should program the static MAC table with the entries that it needs to receive (e.g.,
BPDU packets). The “overriding” bit should be set so that the switch will forward those specific packets to the
processor. The processor may send packets to the port(s) in this state, see “Tail Tagging Mode” section for details.
Address learning is enabled on the port in this state.
Rapid Spanning Tree Support
There are three operational states of Discarding, Learning, and Forwarding assigned to each port for RSTP:
Discarding ports do not participate in the active topology and do not learn MAC addresses.
Discarding state: the state includes three states of the disable, blocking and listening of STP.
Port setting: "transmit enable = 0, receive enable = 0, learning disable = 1."
Software action: the processor should not send any packets to the port. The switch may still send specific packets to
the processor (packets that match some entries in the static table with “overriding bit” set) and the processor should
discard those packets. When disabling the port’s learning capability (learning disable = ’1’), set the register 1 bit 5
and bit 4 will flush rapidly with the port related entries in the dynamic MAC table and static MAC table.
Note: the processor is connected to Port 5 via MII interface. Address learning is disabled on the port in this state.
Ports in Learning states learn MAC addresses, but do not forward user traffic.
Learning state: only packets to and from the processor are forwarded. Learning is enabled.
Port setting: “transmit enable = 0, receive enable = 0, learning disable = 0.”
Software action: The processor should program the static MAC table with the entries that it needs to receive (e.g.,
BPDU packets). The “overriding” bit should be set so that the switch will forward those specific packets to the
processor. The processor may send packets to the port(s) in this state, see “Tail Tagging Mode” section for details.
Address learning is enabled on the port in this state.
Ports in Forwarding states fully participate in both data forwarding and MAC learning.
Forwarding state: packets are forwarded and received normally. Learning is enabled.
Port setting: “transmit enable = 1, receive enable = 1, learning disable = 0.”
Software action: The processor should program the static MAC table with the entries that it needs to receive (e.g.,
BPDU packets). The “overriding” bit should be set so that the switch will forward those specific packets to the
processor. The processor may send packets to the port(s) in this state, see “Tail Tagging Mode” section for details.
Address learning is enabled on the port in this state.
RSTP uses only one type of BPDU called RSTP BPDUs. They are similar to STP Configuration BPDUs with the
exception of a type field set to “version 2” for RSTP and “version 0” for STP, and a flag field carrying additional
information.
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Tail Tagging Mode
The Tail Tag is only seen and used by the Port 5 interface, which should be connected to a processor by SW5MII/RMII interface. The one byte tail tagging is used to indicate the source/destination port in Port 5. Only bit [3−0]
are used for the destination in the tail tagging byte. Other bits are not used. The Tail Tag feature is enabled by setting
register 12 bit 1.
Figure 12. Tail Tag Frame Format
Ingress to Port 5 (Host --> KSZ8895MQ/RQ/FMQ)
Bit [3:0]
Destination
0,0,0,0
Reserved
0,0,0,1
Port 1 (direct forward to Port1)
0,0,1,0
Port 2 (direct forward to Port2)
0,1,0,0
Port 3 (direct forward to Port3)
1,0,0,0
Port 4 (direct forward to Port4)
1,1,1,1
Port 1, 2,3 and 4 (direct forward to Port 1,2,3,4,)
Bit[7:4]
0,0,0,0
Queue 0 is used at destination port
0,0,0,1
Queue 1 is used at destination port
0,0,1,0
Queue 2 is used at destination port
0,0,1,1
Queue 3 is used at destination port
x, 1,x,x
Anyhow send packets to specified port in bits [3:0]
1, x,x,x
Bit[6:0] will be ignored as normal (Adress look-up)
Egress from Port 5 (KSZ8895MQ/RQ/FMQ --> Host)
Bit [1:0]
Source
0,0
Port 1 (packets from Port 1)
0,1
Port 2 (packets from Port 2)
1,0
Port 3 (packets from Port 3)
1,1
Port 4 (packets from Port 4)
Table 7. Tail Tag Rules
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IGMP Support
There are two parts involved to support the Internet Group Management Protocol (IGMP) in Layer 2. The first part is
IGMP snooping, the second part is this IGMP packet to be sent back to the subscribed port. Describe them as
follows.
•
IGMP Snooping
The KSZ8895MQ/RQ/FMQ traps IGMP packets and forwards them only to the processor (Port 5 SW5-MII/RMII).
The IGMP packets are identified as IP packets (either Ethernet IP packets, or IEEE 802.3 SNAP IP packets) with
IP version = 0x4 and protocol version number = 0x2. Set register 5 bit [6] to ‘1’ to enable IGMP snooping.
•
IGMP Send Back to the Subscribed Port
Once the host responds the received IGMP packet, the host should know the original IGMP ingress port and send
back the IGMP packet to this port only, otherwise this IGMP packet will be broadcasted to all port to downgrade
the performance.
Enable the tail tag mode, the host will know the IGMP packet received port from tail tag bits [1:0] and can send
back the response IGMP packet to this subscribed port by setting the bits [3:0] in the tail tag. Enable “Tail tag
mode” by setting Register 12 bit 1.
Port Mirroring Support
The KSZ8895MQ/RQ/FMQ supports “port mirror” comprehensively as:
•
•
•
“Receive Only” mirror on a port
All the packets received on the port will be mirrored on the sniffer port. For example, Port 1 is programmed to be
“rx sniff,” and Port 5 is programmed to be the “sniffer port.” A packet, received on Port 1, is destined to Port 4
after the internal look-up. The KSZ8895MQ/RQ/FMQ will forward the packet to both Port 4 and Port 5.
KSZ8895MQ/RQ/FMQ can optionally forward even “bad” received packets to Port 5.
“Transmit Only” mirror on a port
All the packets transmitted on the port will be mirrored on the sniffer port. For example, Port 1 is programmed to
be “tx sniff,” and Port 5 is programmed to be the “sniffer port.” A packet, received on any of the ports, is destined
to Port 1 after the internal look-up. The KSZ8895MQ/RQ/FMQ will forward the packet to both Ports 1 and 5.
“Receive and Transmit” mirror on two ports.
All the packets received on port A AND transmitted on port B will be mirrored on the sniffer port. To turn on the
“AND” feature, set Register 5 bit 0 to 1. For example, Port 1 is programmed to be “rx sniff,” Port 2 is programmed
to be “transmit sniff,” and Port 5 is programmed to be the “sniffer port.” A packet, received on Port 1, is destined
to Port 4 after the internal look-up. The KSZ8895MQ/RQ/FMQ will forward the packet to Port 4 only, since it does
not meet the “AND” condition. A packet, received on Port 1, is destined to Port 2 after the internal look-up. The
KSZ8895MQ/RQ/FMQ will forward the packet to both Port 2 and Port 5.
Multiple ports can be selected to be “rx sniffed” or “tx sniffed.” And any port can be selected to be the “sniffer port.”
All these per port features can be selected through Register 17.
VLAN Support
The KSZ8895MQ/RQ/FMQ supports 128 active VLANs and 4096 possible VIDs specified in IEEE 802.1q.
KSZ8895MQ/RQ/FMQ provides a 128-entry VLAN table, which correspond to 4096 possible VIDs and converts to
FID (7 bits) for address look-up max 128 active VLANs. If a non-tagged or null-VID-tagged packet is received, then
the ingress port VID is used for look-up when 802.1q is enabled by the global register 5 control 3 bit 7. In the VLAN
mode, the look-up process starts from VLAN table look-up to determine whether the VID is valid. If the VID is not
valid, the packet will then be dropped and its address will not be learned. If the VID is valid, FID is retrieved for
further look-up by the static MAC table or dynamic MAC table. FID+DA is used to determine the destination port. The
following table describes the different actions in different situations of DA and FID+DA in the static MAC table and
dynamic MAC table after the VLAN table finish a look-up action. FID+SA is used for learning purposes. The following
table also describes learning in the dynamic MAC table when the VLAN table has done a look-up in the static MAC
table without a valid entry.
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DA found in
Static MAC table
USE FID
Flag?
FID Match?
DA+FID found in
Dynamic MAC table
No
Do Not care
Do Not care
No
No
Do Not care
Do Not care
Yes
Yes
0
Do Not care
Do Not care
Yes
1
No
No
Yes
1
No
Yes
Yes
1
Yes
Do Not care
Action
Broadcast to the membership ports defined in
the VLAN table bit[11:7].
Send to the destination port defined in the
dynamic MAC table bit[58:56].
Send to the destination port(s) defined in the
static MAC table bit[52:48].
Broadcast to the membership ports defined in
the VLAN table bit[11:7].
Send to the destination port defined in the
dynamic MAC table bit[58:56].
Send to the destination port(s) defined in the
static MAC table bit[52:48].
Table 8. FID+DA Look-Up in the VLAN Mode
SA+FID found in
Dynamic MAC table
Action
No
The SA+FID will be learned into the dynamic table.
Yes
Time stamp will be updated.
Table 9. FID+SA Look-Up in the VLAN Mode
Advanced VLAN features are also supported in KSZ8895MQ/RQ/FMQ, such as “VLAN ingress filtering” and “discard
non PVID” defined in bits [6:5] of the port Register Control 2. These features can be controlled on a port basis.
Rate Limiting Support
The KSZ8895MQ/RQ/FMQ provides a fine resolution hardware rate limiting. The rate step is 64Kbps when the rate
limit is less than 1Mbps rate for 100BT or 10BT. The rate step is 1Mbps when the rate limit is more than 1Mbps rate
for 100BT or 10BT (refer to Data Rate Selection Table which follow the end of the Port Register Queue 0−3
Ingress/Egress Limit Control section). The rate limit is independently on the “receive side” and on the “transmit side”
on a per port basis. For 10BASE-T, a rate setting above 10 Mbps means the rate is not limited. On the receive side,
the data receive rate for each priority at each port can be limited by setting up Ingress Rate Control Registers. On the
transmit side, the data transmit rate for each priority queue at each port can be limited by setting up Egress Rate
Control Registers. The size of each frame has options to include minimum IFG (Inter Frame Gap) or Preamble byte,
in addition to the data field (from packet DA to FCS).
Ingress Rate Limit
For ingress rate limiting, KSZ8895MQ/RQ/FMQ provides options to selectively choose frames from all types,
multicast, broadcast, and flooded unicast frames by bits [3−2] of the port rate limit control register. The
KSZ8895MQ/RQ/FMQ counts the data rate from those selected type of frames. Packets are dropped at the ingress
port when the data rate exceeds the specified rate limit or the flow control takes effect without packet dropped when
the ingress rate limit flow control is enabled by the port rate limit control register bit 4. The ingress rate limiting
supports the port-based, 802.1p and DiffServ-based priorities, the port-based priority is fixed priority 0−3 selection by
bits [4-3] of the port register control 0. The 802.1p and DiffServ-based priority can be mapped to priority 0−3 by
default of the register 128 and 129. In the ingress rate limit, set register 135 global control 19 bit 3 to enable queuebased rate limit if using two-queue or four-queue mode. All related ingress ports and egress port should be split to
two-queue or four-queue mode by the port registers control 9 and control 0. The four-queue mode will use Q0−Q3 for
priority 0−3 by bit[6−0] of the port register ingress limit control 1−4. The two-queue mode will use Q0−Q1 for priority
0-1by bit[6-0] of the port register ingress limit control 1−2. The priority levels in the packets of the 802.1p and DiffServ
can be programmed to priority 0−3 by the register 128 and 129 for a re-mapping.
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Egress Rate Limit
For egress rate limiting, the Leaky Bucket algorithm is applied to each output priority queue for shaping output traffic.
Interframe gap is stretched on a per frame base to generate smooth, non-burst egress traffic. The throughput of each
output priority queue is limited by the egress rate specified by the data rate selection table followed the egress rate
limit control registers.
If any egress queue receives more traffic than the specified egress rate throughput, packets may be accumulated in
the output queue and packet memory. After the memory of the queue or the port is used up, packet dropping or flow
control will be triggered. As a result of congestion, the actual egress rate may be dominated by flow control/dropping
at the ingress end, and may be therefore slightly less than the specified egress rate. The egress rate limiting
supports the port-based, 802.1p and DiffServ-based priorities, the port-based priority is fixed priority 0−3 selection by
bits[4−3] of the port register control 0. The 802.1p and DiffServ-based priority can be mapped to priority 0−3 by
default of the register 128 and 129. In the egress rate limit, set register 135 global control 19 bit 3 for queue-based
rate limit to be enabled if using two-queue or four-queue mode. All related ingress ports and egress port should be
split to two-queue or four-queue mode by the port registers control 9 and control 0. The four-queue mode will use
Q0-Q3 for priority 0−3 by bit[6-0] of the port register egress limit control 1−4. The two-queue mode will use Q0-Q1 for
priority 0−1by bit[6−0] of the port register egress limit control 1−2. The priority levels in the packets of the 802.1p and
DiffServ can be programmed to priority 0−3 by the register 128 and 129 for a re-mapping.
When the egress rate is limited, just use one queue per port for the egress port rate limit. The priority packets will be
based upon the data rate selection table (see Tables 13 and 14). If the egress rate limit uses more than one queue
per port for the egress port rate limit, then the highest priority packets will be based upon the data rate selection table
for the rate limit exact number. Other lower priority packet rates will be limited based upon 8:4:2:1 (default) priority
ratio, which is based on the highest priority rate. The transmit queue priority ratio is programmable.
To reduce congestion, it is good practice to make sure the egress bandwidth exceeds the ingress bandwidth.
Transmit Queue Ratio Programming
In transmit queues 0−3 of the egress port, the default priority ratio is 8:4:2:1. The priority ratio can be programmed by
the port registers control 10, 11, 12 and 13. When the transmit rate exceeds the ratio limit in the transmit queue, the
transmit rate will be limited by the transmit queue 0−3 ratio of the port register control 10, 11, 12 and 13. The highest
priority queue will not be limited. Other lower priority queues will be limited based on the transmit queue ratio.
Filtering for Self-Address, Unknown Unicast/Multicast Address and Unknown VID Packet/IP Multicast
Enable Self-address filtering, the unknown unicast packet filtering and forwarding by the Register 131 Global Control
15. Enable Unknown multicast packet filtering and forwarding by the Register 132 Global Control 16.
Enable Unknown VID packet filtering and forwarding by the Register 133 Global Control 17.
Enable Unknown IP multicast packet filtering and forwarding by the Register 134 Global Control 18.
This function is very useful in preventing packets that could degrade the quality of the port in applications such as
voice over Internet Protocol (VoIP) and the daisy chain connection.
Configuration Interface
2
I C Master Serial Bus Configuration
If a 2-wire EEPROM exists, then the KSZ8895MQ/RQ/FMQ can perform more advanced features like broadcast
storm protection and rate control. The EEPROM should have the entire valid configuration data from Register 0 to
Register 255 defined in the “Memory Map,” except the chipID = 0 in the register1 and the status registers. After reset,
the KSZ8895MQ/RQ/FMQ will start to read all 255 registers sequentially from the EEPROM. The configuration
access time (tprgm) is less than 30ms, as shown in Figure 8.
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Figure 13. KSZ8895MQ/RQ/FMQ EEPROM Configuration Timing Diagram
To configure the KSZ8895MQ/RQ/FMQ with a pre-configured EEPROM use the following steps:
1. At the board level, connect pin 110 on the KSZ8895MQ/RQ/FMQ to the SCL pin on the EEPROM. Connect pin
111 on the KSZ8895MQ/RQ/FMQ to the SDA pin on the EEPROM.
2. A[2-0] address pins of EEPROM should be tied to ground for address A[2-0] = ‘000’ to be identified by the
KSZ8895MQ/RQ/FMQ.
3. Set the input signals PS[1:0] (pins 113 and 114, respectively) to “00.” This puts the KSZ8895MQ/RQ/FMQ serial
2
bus configuration into I C master mode.
4. Be sure the board-level reset signal is connected to the KSZ8895MQ/RQ/FMQ reset signal on pin 115 (RST_N).
5. Program the contents of the EEPROM before placing it on the board with the desired configuration data. Note
that the first byte in the EEPROM must be “95” for the loading to occur properly. If this value is not correct, all
other data will be ignored.
6. Place EEPROM on the board and power up the board. Assert the active-low board level reset to RST_N on the
KSZ8895MQ/RQ/FMQ. After the reset is de-asserted, the KSZ8895MQ/RQ/FMQ will begin reading configuration
data from the EEPROM. The configuration access time (tprgm) is less than 30ms.
Note: For proper operation, make sure that pin 47 (PWRDN_N) is not asserted during the reset operation.
SPI Slave Serial Bus Configuration
The KSZ8895MQ/RQ/FMQ can also act as a SPI slave device. Through the SPI, the entire feature set can be
enabled, including “VLAN,” “IGMP snooping,” “MIB counters,” etc. The external master device can access any
register from Register 0 to Register 255 randomly. The system should configure all the desired settings before
enabling the switch in the KSZ8895MQ/RQ/FMQ. To enable the switch, write a "1" to Register 1 bit 0.
Two standard SPI commands are supported (00000011 for “READ DATA,” and 00000010 for “WRITE DATA”). To
speed configuration time, the KSZ8895MQ/RQ/FMQ also supports multiple reads or writes. After a byte is written to
or read from the KSZ8895MQ/RQ/FMQ, the internal address counter automatically increments if the SPI Slave
Select Signal (SPIS_N) continues to be driven low. If SPIS_N is kept low after the first byte is read, the next byte at
the next address will be shifted out on SPIQ. If SPIS_N is kept low after the first byte is written, bits on the Master
Out Slave Input (SPID) line will be written to the next address. Asserting SPIS_N high terminates a read or write
operation. This means that the SPIS_N signal must be asserted high and then low again before issuing another
command and address. The address counter wraps back to zero once it reaches the highest address. Therefore the
entire register set can be written to or read from by issuing a single command and address.
The default SPI clock speed is 12.5MHz. The KSZ8895MQ/RQ/FMQ is able to support a SPI bus up to 25MHz (set
register 12 bit[5:4] = 0x10). A high performance SPI master is recommended to prevent internal counter overflow.
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To use the KSZ8895MQ/RQ/FMQ SPI:
1. At the board level, connect KSZ8895MQ/RQ/FMQ pins as follows:
KSZ8895MQ/RQ/FMQ
Pin Number
KSZ8895MQ/RQ/FMQ
Signal Name
112
SPIS_N
110
SPIC
SPI Clock
111
SPID
Master Out Slave Input
109
SPIQ
Master In Slave Output
Microprocessor Signal Description
SPI Slave Select
Table 10. SPI Connections
2. Set the input signals PS[1:0] (pins 113 and 114, respectively) to “10” to set the serial configuration to SPI slave
mode.
3. Power up the board and assert a reset signal. After reset wait 100µs, the start switch bit in Register 1 will be set
to ‘0’. Configure the desired settings in the KSZ8895MQ/RQ/FMQ before setting the start register to ‘1.'
4. Write configuration to registers using a typical SPI write data cycle as shown in Figure 9 or SPI multiple write as
shown in Figure 11. Note that data input on SPID is registered on the rising edge of SPIC.
5. Registers can be read and configuration can be verified with a typical SPI read data cycle as shown in Figure 10
or a multiple read as shown in Figure 12. Note that read data is registered out of SPIQ on the falling edge of
SPIC.
6. After configuration is written and verified, write a ‘1’ to Register 1 bit 0 to begin KSZ8895MQ/RQ/FMQ switch
operation.
SPIS_N
SPIC
SPID
X
0
0
0
0
0
0
1
0
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SPIQ
WRITE COMMAND
WRITE ADDRESS
WRITE DATA
Figure 14. SPI Write Data Cycle
SPIS_N
SPIC
SPID
X
0
0
0
0
0
0
1
1
A7
A6
A5
A4
A3
A2
SPIQ
A1
A0
D7
READ COMMAND
READ ADDRESS
D6
D5
D4
D3
D2
D1
D0
READ DATA
Figure 15. SPI Read Data Cycle
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SPIS_N
SPIC
SPID
X
A1
A2
A3
A4
A5
A6
A7
0
1
0
0
0
0
0
0
A0
D7
D6
D5
D4
D3
D2
D1
D0
D2
D1
D0
SPIQ
WRITE COMMAND
WRITE ADDRESS
Byte 1
SPIS_N
SPIC
SPID
D7
D6
D5
D4
D4
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D7
D0
D6
D5
D4
D3
SPIQ
Byte 2
Byte N
Byte 3 ...
Figure 16. SPI Multiple Write
SPIS_N
SPIC
SPID
X
0
0
0
0
0
0
1
1
A7
A6
A5
A4
A3
A2
A1
SPIQ
A0
X
X
X
X
X
X
X
X
D7
D6
D5
D4
D3
D2
D1
D0
READ ADDRESS
READ COMMAND
Byte 1
SPIS_N
SPIC
SPID
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SPIQ
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Byte 2
Byte 3 ...
Byte N
Figure 17. SPI Multiple Read
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MII Management Interface (MIIM)
The KSZ8895MQ/RQ/FMQ supports the standard IEEE 802.3 MII Management Interface, also known as the
Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control
the states of the KSZ8895MQ/RQ/FMQ. An external device with MDC/MDIO capability is used to read the PHY
status or configure the PHY settings. Further details on the MIIM interface are found in Clause 22.2.4.5 of the IEEE
802.3u Specification.
The MIIM interface consists of the following:
•
A physical connection that incorporates the data line (pin 108 MDIO) and the clock line (pin 107 MDC).
•
A specific protocol that operates across the aforementioned physical connection that allows an external
controller to communicate with the KSZ8895MQ/RQ/FMQ device.
•
Access to a set of eight 16-bit registers, consisting of 8 standard MIIM registers [0:5h], 1d and 1f MIIM
registers per port.
The MIIM Interface can operate up to a maximum clock speed of 10MHz MDC clock.
Table 11 depicts the MII Management Interface frame format.
Preamble
Start of
Frame
Read/Write
OP Code
PHY
Address
Bits[4:0]
REG
Address
Bits[4:0]
TA
Data Bits[15:0]
Idle
Read
32 1’s
01
10
AAAAA
RRRRR
Z0
DDDDDDDD_DDDDDDDD
Z
Write
32 1’s
01
01
AAAAA
RRRRR
10
DDDDDDDD_DDDDDDDD
Z
Table 11. MII Management Interface Frame Format
The MIIM interface does not have access to all the configuration registers in the KSZ8895MQ/RQ/FMQ. It can only
access the standard MIIM registers. See “MIIM Registers”. The SPI interface and MDC/MDIO SMI mode, on the
other hand, can be used to access all registers with the entire KSZ8895MQ/RQ/FMQ feature set.
Serial Management Interface (SMI)
The SMI is the KSZ8895MQ/RQ/FMQ non-standard MIIM interface that provides access to all KSZ8895MQ/RQ/FMQ
configuration registers. This interface allows an external device with MDC/MDIO interface to completely monitor and
control the states of the KSZ8895MQ/RQ/FMQ.
The SMI interface consists of the following:
•
A physical connection that incorporates the data line (MDIO) and the clock line (MDC).
•
A specific protocol that operates across the aforementioned physical connection that allows an external controller
to communicate with the KSZ8895MQ/RQ/FMQ device.
•
Access to all KSZ8895MQ/RQ/FMQ configuration registers. Register access includes the Global, Port and
Advanced Control Registers 0-255 (0x00 – 0xFF), and indirect access to the standard MIIM registers [0:5] and
custom MIIM registers [29, 31].
The SMI Interface can operate up to a maximum clock speed of 10MHz MDC clock.
Table 12 depicts the SMI frame format.
Preamble
Start of
Frame
Read/Write
OP Code
PHY
REG
Address
Address
Bits[4:0]
Bits[4:0]
TA
Data Bits[15:0]
Idle
Read
32 1’s
01
10
RR11R
RRRRR
Z0
0000_0000_DDDD_DDDD
Z
Write
32 1’s
01
01
RR11R
RRRRR
10
xxxx_xxxx_DDDD_DDDD
Z
Table 12. Serial Management Interface (SMI) Frame Format
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KSZ8895MQ/RQ/FMQ
SMI register Read access is selected when OP Code is set to “10” and bits [2:1] of the PHY address is set to ‘11’.
The 8-bit register address is the concatenation of {PHY address bits [4:3], PHY address bits [0], REG address bit
[4:0]}. TA is turn-around bits. TA bits [1:0] are ’Z0’ means the processor MDIO pin is changed to input Hi-Z from
output mode and the followed ‘0’ is the read response from device, as the switch configuration registers are 8-bit
wide, only the lower 8 bits of data bits [15:0] are used
SMI register Write access is selected when OP Code is set to “01” and bits [2:1] of the PHY address is set to ‘11’.
The 8-bit register address is the concatenation of {PHY address bits [4:3], PHY address bits [0], REG address bit
[4:0]}. TA bits [1:0] are set to ’10’, as the switch configuration registers are 8-bit wide, only the lower 8 bits of data bits
[15:0] are used.
To access the KSZ8895MQ/RQ/FMQ registers 0-255 (0x00 - 0xFF), the following applies:
PHYAD [4, 3, 0] and REGAD [4:0] are concatenated to form the 8-bit address; that is, {PHYAD [4, 3, 0], REGAD
[4:0]} = bits [7:0] of the 8-bit address.
Registers are 8 data bits wide. For read operation, data bits [15:8] are read back as zeroes. For write operation, data
bits [15:8] are not defined, and hence can be set to either zeroes or ones.
SMI register access is the same as the MIIM register access, except for the register access requirements presented
in this section.
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KSZ8895MQ/RQ/FMQ
Register Description
Offset
Decimal
Hex
Description
0−1
0x00-0x01
Chip ID Registers.
2−13
0x02-0x0D
Global Control Registers.
14−15
0x0E-0x0F
Power Down Management Control Registers.
16−20
0x10-0x14
Port 1 Control Registers.
21−24
0x15-0x18
Port 1 Reserved (Factory Test Registers).
25−31
0x19-0x1F
Port 1 Control/Status Registers.
32−36
0x20-0x24
Port 2 Control Registers.
37−40
0x25-0x28
Port 2 Reserved (Factory Test Registers).
41−47
0x29-0x2F
Port 2 Control/Status Registers.
48−52
0x30-0x34
Port 3 Control Registers.
53−56
0x35-0x38
Port 3 Reserved (Factory Test Registers).
57−63
0x39-0x3F
Port 3 Control/Status Registers.
64−68
0x40-0x44
Port 4 Control Registers.
69−72
0x45-0x48
Port 4 Reserved (Factory Test Registers).
73−79
0x49-0x4F
Port 4 Control/Status Registers.
80−84
0x50-0x54
Port 5 Control Registers.
85−88
0x55-0x58
Port 5 Reserved (Factory Test Registers).
89−95
0x59-0x5F
Port 5 Control/Status Registers.
96−103
0x60-0x67
Reserved (Factory Testing Registers).
104−109
0x68-0x6D
MAC Address Registers.
110−111
0x6E-0x6F
Indirect Access Control Registers.
112−120
0x70-0x78
Indirect Data Registers.
121−123
0x79-0x7B
Reserved (Factory Testing Registers).
124−125
0x7C-0x7D
Port Interrupt Registers.
126−127
0x7E-0x7F
Reserved (Factory Testing Registers).
128−135
0x80-0x87
Global Control Registers.
136
0x88
Reserved for Factory Testing.
137−143
0x89-0x8F
Reserved for Factory.
144−145
0x90-0x91
TOS Priority Control Registers.
146−159
0x92-0x9F
TOS Priority Control Registers.
160−175
0xA0-0xAF
Reserved (Factory Testing Registers).
176−190
0xB0-0xBE
Port 1 Control Registers.
191
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0xBF
Reserved (Factory Testing Register): Transmit Queue Remap Base Register.
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KSZ8895MQ/RQ/FMQ
Register Description (Continued)
Offset
Decimal
192−206
Hex
0xC0-0xCE
207
208−222
0xCF
0xD0-0xDE
223
224−238
0xDF
0xE0-0xEE
239
240−254
Description
0xEF
0xF0-0xFE
255
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0xFF
Port 2 Control Registers.
Reserved (Factory Testing Register).
Port 3 Control Registers.
Reserved (Factory Testing Register).
Port 4 Control Registers.
Reserved (Factory Testing Register).
Port 5 Control Registers.
Reserved (Factory Testing Register).
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KSZ8895MQ/RQ/FMQ
Global Registers
Address
Name
Description
Mode
Default
Chip family.
RO
0x95
0100 = KSZ8895MQ/FMQ
0110 = KSZ8995RQ
RO
0x4 is for
MQ/FMQ
0x6 is RQ
Revision ID
RO
0x0
Register 0 (0x00): Chip ID0
7−0
Family ID
Register 1 (0x01): Chip ID1 / Start Switch
7−4
Chip ID
3−1
Revision ID
0
Start Switch
1, start the chip when external pins (PS1, PS0) = (1,0)
Note: in (PS1,PS0) = (0,0) mode, the chip will
start automatically, after trying to read the external
EEPROM. If EEPROM does not exist, the chip will use
default values for all internal registers. If EEPROM is
present, the contents in the EEPROM will be checked.
The switch will check:
7 Register 0 = 0x95,
(2) Register 1 [7:4] = Availible chip ID.
If this check is OK, the contents in the EEPROM will
override chip register default values =0, chip will not
start when external pins
(PS1, PS0) = (1,0) or (0,1).
R/W
0
Note: (PS1, PS0) = (1,1) for Factory test only.
0, stop the switch function of the chip.
Register 2 (0x02): Global Control 0
7
New Back-off Enable
New Back-off algorithm designed for UNH
1 = Enable
0 = Disable
R/W
0
6
Reserved
Reserved.
RO
0
R/W
(SC)
0
R/W
(SC)
0
Flush the entire dynamic MAC table for RSTP
1 = Trigger the flush dynamic MAC table operation.
This bit is self clear
0 = normal operation
5
Flush dynamic MAC table
Note: All the entries associated with a port that has its
learning capability being turned off (Learning Disable)
will be flushed. If you want to flush the entire Table, all
ports learning capability must be turned off.
Flush the matched entries in static MAC table for RSTP
1 = Trigger the flush static MAC table operation. This
bit is self clear
0 = normal operation
4
Flush static MAC table
March 12, 2014
Note: The matched entry is defined as the entry whose
Forwarding Ports field contains a single port and MAC
address with unicast. This port, in turn, has its learning
capability being turned off (Learning Disable). Per port,
multiple entries can be qualified as matched entries.
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KSZ8895MQ/RQ/FMQ
Global Registers (Continued)
Address
Name
3
Enable PHY MII/RMII
2
Reserved
1
UNH Mode
0
Link Change Age
Description
Mode
Default
1, enable PHY P5-MII/RMII interface (default).
Note: if not enabled, the switch will tri-state all outputs.
R/W
1
Pin LED[5][1]
strap option.
PD(0): isolate.
PU(1): Enable.
Note: LED[5][1]
has internal pullup (PU).
N/A Do not change.
RO
1
R/W
0
R/W
0
R/W
0
R/W
0
1, the switch will drop packets with 0x8808 in T/L filed,
or DA = 01-80-C2-00-00-01.
0, the switch will drop packets qualified as “flow control”
packets.
1, link change from “link” to “no link” will cause fast
aging (
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